As semiconductor device manufacturing technology continues to evolve, new manufacturing processes and/or device structures such as, for example, replacement-metal-gate (RMG) and self-aligned-contact (SAC) are being introduced and applied to devices and in particular in smaller node environment such as, for example, 10 nm node and beyond. As a result, currently existing technologies of manufacturing metal resistor and electronic-fuse (e-fuse), that are mainly adapted for manufacturing devices up to 20 nm and 14 nm node, become incompatible with the newly introduced processes and/or structures of RMG and/or SAC.
For example, in a conventional 14 nm node manufacturing process, metal resistor and/or e-fuse are typically made through, for example, steps of forming or depositing a tungsten silicide (WSix) layer on top of a blanket nitride cap layer and patterning the tungsten silicide layer, for example through a photolithographic patterning process, into a desired shape or shapes which eventually form resistor and/or e-fuse, depending on their specific application. However, in a 10 nm RMG process, steps are performed to create metal recess, deposit nitride material in the recess, and subsequently polish the nitride material to create nitride cap. It is obvious that, due to the nature of applying a reactive-ion-etching (RIE) process in forming self-aligned contact, a separate step of blank nitride deposition no longer exists to be even available for the purpose of forming metal resistor and/or e-fuse, as opposed to be in a conventional process for a 14 nm node.